1. Field of the Invention
This invention relates to an integrated circuit in which a plurality of digital functional blocks are provided with a parity check system or some other form of redundancy and an error detecting circuit is provided for all or some of the functional blocks and which is designed so that the result of operation of the error detecting circuit can be provided to the outside.
2. Description of the Prior Art
One method that has heretofore been employed for diagnosing a combinatorial or sequential circuit is, for instance, a method using a fault simulator. This conventional method of diagnosis is relatively easy to employ for an integrated circuit having several thousand gates. However, in the case of an integrated circuit having dozens to hundreds of thousand gates as a result of increased integration density, it is assumed that the conventional diagnosing method using the fault simulator would impose a great burden on the operation of the integrated circuit.